Manual browser: TC_DENSE_TO_SPARSE(9)
|TC(9)||Kernel Developer's Manual||TC(9)|
NAMETC, tc_intr_establish, tc_intr_disestablish, tc_intr_evcnt. tc_mb, tc_wmb, tc_syncbus, tc_badaddr, TC_DENSE_TO_SPARSE, TC_PHYS_TO_UNCACHED — TURBOchannel bus
tc_intr_establish(struct device *dev, void *cookie, int level, int (*handler)(void *), void *arg);
tc_intr_disestablish(struct device *dev, void *cookie);
const struct evcnt *
tc_intr_evcnt(struct device *dev, void *cookie);
DESCRIPTIONThe TC device provides support for the DEC TURBOchannel bus found on all DEC TURBOchannel machines with MIPS (DECstation 5000 series, excluding the 5000/200) and Alpha (3000-series) systems. TURBOchannel is a 32-bit wide synchronous DMA-capable bus, running at 25 MHz on higher-end machines and at 12.5 MHz on lower-end machines.
DATA TYPESDrivers for devices attached to the TURBOchannel bus will make use of the following data types:
- struct tc_attach_args
A structure use to inform the driver of TURBOchannel bus properties. It contains the following members:
bus_space_tag_t ta_memt; bus_dma_tag_t ta_dmat; char ta_modname[TC_ROM_LLEN+1]; u_int ta_slot; tc_offset_t ta_offset; tc_addr_t ta_addr; void *ta_cookie; u_int ta_busspeed;
The ta_busspeed member specifies the TURBOchannel bus speed and is useful for time-related functions. Values values are TC_SPEED_12_5_MHZ for the 12.5 MHz bus and TC_SPEED_25_MHZ for the 50 MHz bus.
- tc_intr_establish(dev, cookie, level, handler, arg)
- Establish an interrupt handler with device dev for the interrupt described completely by cookie, the value passed to the driver in the ta_cookie member of the tc_attach_args structure. The priority of the interrupt is specified by level. When the interrupt occurs the function handler is called with argument arg.
- tc_intr_disestablish(dev, cookie)
- Dis-establish the interrupt handler with device dev for the interrupt described completely cookie.
- tc_intr_evcnt(dev, cookie)
- Do interrupt event counting with device dev for the event described completely by cookie.
- A read/write memory barrier. Any CPU-to-memory reads/writes before the barrier must complete before any CPU-to-memory reads/writes after it.
- A write memory barrier. Any CPU-to-memory writes before the barrier must complete before any CPU-to-memory writes after it.
- Synchronise writes on the TURBOchannel bus by ensuring CPU writes are propagated across the TURBOchannel bus.
- Returns non-zero if the given address tcaddr is invalid.
- Convert the given physical address addr in TURBOchannel dense space to the corresponding address in TURBOchannel sparse space.
- Convert the given system memory physical address addr to the physical address of the corresponding region that is not cached.
AUTOCONFIGURATIONThe TURBOchannel bus is a direct-connection bus. During autoconfiguration, the parent specifies the name of the found TURBOchannel module into the ta_modname member of the tc_attach_args structure. Drivers should match on this name.
DMA SUPPORTThe TURBOchannel bus supports 32-bit, bidirectional DMA transfers. Support is provided by the standard bus_dma(9) interface.
CODE REFERENCESThe TURBOchannel subsystem itself is implemented within the file sys/dev/tc/tc_subr.c. Machine-dependent portions can be found in sys/arch/<arch>/tc/tcbus.c.
|October 7, 2001||NetBSD 7.0|