Manual browser: ioasic(9)
|IOASIC(9)||Kernel Developer's Manual||IOASIC(9)|
NAMEIOASIC, ioasic_intr_establish, ioasic_intr_disestablish, ioasic_intr_evcnt, ioasic_attach_devs, ioasic_submatch — baseboard I/O control ASIC for DEC TURBOchannel systems
ioasic_intr_establish(struct device *dev, void *cookie, int level, int (*handler)(void *), void *arg);
ioasic_intr_disestablish(struct device *dev, void *cookie);
const struct evcnt *
ioasic_intr_evcnt(struct device *dev, void *cookie);
ioasic_attach_devs(struct ioasic_softc *sc, struct ioasic_dev *ioasic_devs, int ioasic_ndevs);
ioasic_submatch(struct cfdata *match, struct ioasicdev_attach_args *ia);
DESCRIPTIONThe IOASIC device provides support for the DEC proprietary IOCTL ASIC found on all DEC TURBOchannel machines with MIPS (DECstation 5000 series, excluding the 5000/200) and Alpha (3000-series) systems. The IOASIC is memory-mapped into the TURBOchannel system slot to interface up to sixteen I/O devices. It connects the TURBOchannel to a 16-bit wide I/O bus and supplies various control signals to the devices that share this bus.
The IOASIC provides hardware DMA channels and interrupt support. DMA transfers are between one and four 32-bit words (16 bytes) in length, depending on the device. The IOASIC stores the data in internal data registers. The data is transferred to and from the registers in 16-bit words to the device. Various interrupts are signalled on DMA pointer-related conditions.
DATA TYPESDrivers for devices attached to the IOASIC will make use of the following data types:
- struct ioasicdev_attach_args
A structure used to inform the driver of the IOASIC device properties. It contains the following members:
char iada_modname tc_offset_t iada_offset tc_addr_t iada_addr void *iada_cookie;
- struct ioasic_softc
The parent structure which contains at the following members which are useful for drivers:
bus_space_tag_t sc_bst; bus_space_handle_t sc_bsh; bus_dma_tag_t sc_dmat;
- struct ioasic_dev
A structure describing the machine-dependent devices attached to the IOASIC containing the following members:
char *iad_modname; tc_offset_t iad_offset; void *iad_cookie; uint32_t iad_intrbits;
- ioasic_intr_establish(dev, cookie, level, handler, arg)
- Establish an interrupt handler with device dev for the interrupt described completely by cookie. The priority of the interrupt is specified by level. When the interrupt occurs the function handler is called with argument arg.
- ioasic_intr_disestablish(dev, cookie)
- Dis-establish the interrupt handler with device dev for the interrupt described complete ly cookie.
- ioasic_intr_evcnt(dev, cookie)
- Do interrupt event counting with device dev for the event described completely by cookie.
- ioasic_attach_devs(sc, ioasic_devs, ioasic_ndevs)
- Configure each of the ioasic_ndevs devices in ioasic_devs.
- ioasic_submatch(match, ia)
- Check that the device offset is not OASIC_OFFSET_UNKNOWN.
The ioasic_intr_establish(), ioasic_intr_disestablish(), and ioasic_intr_evcnt() functions are likely to used by all IOASIC device drivers. The ioasic_attach_devs() function is used by ioasic driver internally and is of interest to driver writers because it must be aware of your device for it to be found during autoconfiguration.
AUTOCONFIGURATIONThe IOASIC is a direct-connection bus. During autoconfiguration, machine-dependent code will provide an array of struct ioasic_devs describing devices attached to the IOASIC to be used by the ioasic driver. The ioasic driver will pass this array to ioasic_attach_devs() to attach the drivers with the devices.
Drivers match the device using iada_modname.
During attach, all drivers should use the parent's bus_space and bus_dma resources, and map the appropriate bus_space region using bus_space_subregion() with iada_offset.
DMA SUPPORTNo additional support is provided for IOASIC DMA beyond the facilities provided by the bus_dma(9) interface.
The IOASIC provides two pairs of DMA address pointers (transmitting and receiving) for each DMA-capable device. The pair of address pointers point to consecutive (but not necessarily contiguous) DMA blocks of size IOASIC_DMA_BLOCKSIZE. Upon successful transfer of the first block, DMA continues to the next block and an interrupt is posted to signal an address pointer update. DMA transfers are enabled and disabled by bits inside the IOASIC status (CSR) register.
The interrupt handler must update the address pointers to point to the next block in the DMA transfer. The address pointer update must be completed before the completion of the second DMA block, otherwise a DMA overrun error condition will occur.
CODE REFERENCESThe IOASIC subsystem itself is implemented within the file sys/dev/tc/ioasic_subr.c. Machine-dependent portions can be found in sys/arch/<arch>/tc/ioasic.c.
|August 6, 2000||NetBSD 7.0|